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内存屏障和cache一致性的关系
2017-7-27
Peter Harris Hi levi,In a coherent multi-core system then data is always kept in sync between the caches, provided the pages are marked as shared in t

CAS (compare and swap)
2026-6-10
CAS是计算机科学中的一个重要概念,用来实现锁机制和原子操作等。先来看一个例子:long v = 0;long count = 1000000;void thread1(){ for (int i = 0; i < count; i++) v++;}void threa

load acquire / store release
2026-6-12
C+11 memory model中提到了relaxed/acquire/release等内存模型。GCC提供了Memory Model Aware Atomic Operations的内置函数 Built-in Functions.原子操作内存模型有:__ATOMIC_RELAXED__ATOMI

on same cacheline, arm may be strong memory order
2026-6-13
众所周知arm是weakly ordered CPU. 参考1给出了详细的例子。也就是说在CPU0: X = 1; Y = 1;CPU1: if (Y == 1) assert(x == 1);由于X = 1; 可能发生在Y = 1; 后面。所以CPU1观察到Y = 1时,X可能还不是1,所以断言会

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